Conventionally, as a method of designing layout of semiconductor integrated circuits, there are three types of design methods: a gate array based design, a full custom design, and a standard-cell based design.
In the gate array based design, transistors that have been regularly arranged beforehand are designed only by a change in interconnection connection. For this reason, it cannot be applied to a semiconductor such as a memory product, in which the degree of integration is pursued.
In the full custom design, a high-performance semiconductor can be designed. However, since a designer manually arranges cells on physical coordinates while viewing a layout pattern, a long period and effort are required for development. Thus, it cannot be applied to a semiconductor that is to be designed in a short period.
The standard-cell based design is the method in which standard-cells are automatically placed. Thus, it is suitable for a semiconductor that is to be designed in a short period, and has been used a lot in recent years. In the conventional automatic placement method of standard-cells, however, the cells are simply placed according to a certain rule, in principle. For this reason, it is not suitable for design in which placement positions of individual cells are optimized to extract their performances. Accordingly, it is difficult to perform design that attaches importance to circuit quality, according to the design method using the standard-cell method. Further, using a technique referred to as grouping, it is possible to define a plurality of cells as one group, and to execute automatic placement of the cells that belong to that group to be close to each other. However, a relative positional relationship for placement of the cells in the same group cannot be specified. For this reason, the placement orders of the cells desired by a circuit designer could not be obtained, so that an optimized circuit could not be designed.
Incidentally, as documents about automated design for a timing constraint, optimized placement, Patent Document 1, for example, proposes a placement method in which a logic cell associated with a critical path and close to input and output terminals of the group are arranged in a more outer divided region, while a logic cell located distant from the input and output terminals is arranged in a more inner divided region. With this placement method, automated placement reflecting a circuit configuration becomes possible, and a design period is reduced while satisfying a timing constraint condition. Patent Document 2 discloses a design method in which a net list indicating a connecting relationship between flip-flops associated with the timing constraint is generated, layout design is performed after arranging positions of the flip-flops are determined according to this net list, thereby securing satisfaction of the timing constraint of an LSI in a short processing time. Patent Document 3 discloses a method of obtaining placement design with less nonuniformity in the distribution density of interconnection in the placement design using the standard-cell method. Patent Document 4 describes a method including a step in which a module is divided in cell placement regions, in each of which internal cells are arranged in a row, and the allotment into the cell row of the internal cells is optimized, thereby optimizing and placement in the cell row of the internal cells. Patent Document 5 discloses a method in which a change in design such as cell insertion, cell exchange, or cell deletion is captured in the course of automated placement design, timing determination, design change, and formation of an placement line loop are performed, thereby performing automatic modification processing in a short period. Further, Patent Document 6 discloses a method in which even in an LSI including a lot of hard macros, high-quality module placement can be implemented without using manpower.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2001-68551A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-10-74842
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-A-10-189750
[Patent Document 4]
Japanese Patent No. 2800781
[Patent Document 5]
Japanese Patent No. 3256597
[Patent Document 6]
Japanese Patent No. 3433025